1. Field of the Invention
This invention relates to a capacitor in a semiconductor memory device and its fabrication method, and more particularly to a capacitor in a semiconductor memory device having a ring-like structure.
2. Background of the Invention
Because electronic and computer products are widely used today, semiconductor memory devices are in great demand. FIG. 1A shows a simplified block diagram of a prior art memory device 14 and its related system. The memory cells of memory 14 are arranged with an array structure consisting of rows and columns. All of the horizontal lines connected with memory 14 are called word lines 11, and all of the vertical lines connected with memory 14 are called bit lines 13. All data accessing is done through bit lines 13.
Row lines 10 and column lines 12 are used to select one of the plurality of addresses in memory 14. The signals in row lines 10 and column lines 12 are registered in row buffers 15 and column buffers 17 respectively. Subsequently, those signals in buffers 15 and 17 are transmitted to row decoder 16 and column decoder 18 to produce the signals into word lines 11 and bit lines 13 for selecting one of the memory cells. Row decoder 16 and column decoder 18 are used to reduce the number of address lines which access memory 14. An array structure such as the memory system mentioned above has advantages for VLSI design and fabrication. FIG. 1B shows a circuit of a DRAM cell which is composed of a transistor 20 and a storage capacitor 22, wherein the gate terminal 20a of transistor 20 is controlled by the signal in word line 11. Capacitor 22 for data storage is connected with source terminal 20c of transistor 20. Data in capacitor 22 are accessible by drain terminal 20b of transistor and bit line 13.
Because of the low cost per bit, the feasibility of high density, and the convenience for read/write, DRAMs have become the semiconductor memory device of choice. However, with increasing DRAM cell density, the area occupied by the capacitor in a DRAM cell and its capacitance necessarily decreases. FIG. 2A shows the cross section of a conventional capacitor in a DRAM cell which comprises a storage electrode 24, a dielectric layer 26, and a plate electrode 28. When the integration size of the DRAM cells becomes smaller due to the advanced fabrication techniques and the higher cell density, the area occupied by the capacitor in a DRAM cell and the capacitance of the capacitor decrease. Many memory accessing errors are caused by exterior radiation. In order to reduce these errors, a sufficient capacitance is required. Therefore, while the miniaturization of the integration size of the DRAM cells continues, it is also necessary to maximize the capacitance of the capacitors to reduce accessing errors.
For the purpose of increasing the capacitance of the capacitors in the DRAM cells, some methods for forming a fingerlike, cylindrical, rectangular multilayer structure, or spacer in polysilicon layers have been proposed to increase the area of the capacitor electrode. FIG. 2B shows the cross section of another conventional capacitor in a DRAM cell which comprises a storage electrode 25, a dielectric layer 27, and a plate electrode 29. Though the area of the capacitor in FIG. 2B is larger than that in FIG. 2A, the fabrication process will be difficult when the size of DRAM cells decrease. Furthermore, the increment in the capacitance gained by increasing the area of the capacitor electrode is insufficient to compensate for the decrement in the capacitance due to the decreasing size of the DRAM cells.